Magnetic memory with phonon glass electron crystal material

ABSTRACT

A magnetic memory unit includes a tunneling barrier separating a free magnetic element and a reference magnetic element. A first phonon glass electron crystal layer is disposed on a side opposing the tunneling barrier of either the free magnetic element or the reference magnetic element. A second phonon glass electron crystal layer also be disposed on a side opposing the tunneling barrier of either the free magnetic element or the reference magnetic element to provide a Peltier effect on the free magnetic element and the reference magnetic element.

RELATED APPLICATIONS

This application is a continuation of U.S. application Ser. No. 13/089,538, filed Apr. 19, 2011, which is a divisional of U.S. application Ser. No. 12/423,119 filed Apr. 14, 2009, issued as U.S. Pat. No. 8,089,132 on Jan. 3, 2012, which claims priority to U.S. provisional patent application No. 61/104,078, filed on Nov. 18, 2008. The entire disclosure these applications are incorporated herein by reference.

BACKGROUND

Magnetic random access memory (MRAM) devices are solid state, non-volatile memory devices which make use of the giant magnetoresistive effect. A conventional MRAM device includes a column of first electrical wires, referred to as word lines, and a row of second electrical wires, referred to as bit lines. An array of magnetic memory cells, located at the junctions of the word lines and bit lines, is used to record data signals.

A magnetic memory cell includes a hard magnetic layer, a soft magnetic layer, and a non-magnetic layer sandwiched between the hard magnetic layer and the soft magnetic layer. The hard magnetic layer has a magnetization vector or orientation fixed in one direction. The orientation of this magnetization vector does not change under a magnetic field or electron spin-torque applied thereon. The soft magnetic layer has an alterable magnetization vector or orientation under a magnetic field applied thereon, that either points to the same direction, hereinafter “parallel alignment”, or to the opposite direction, hereinafter “antiparallel alignment”, of the magnetization vector or orientation of the hard magnetic layer. Since the resistances of the magnetic memory cell in the “parallel alignment” status and the “antiparallel alignment” status are different, the two types of alignment status can be used to record the two logical states—the “0”s or “1”s of a data bit.

In a writing operation for one illustrative embodiment, an electric current passes through the word line and the bit line adjacent to the memory cell. When the electric current reaches a certain threshold, a magnetic field generated by the electric current will switch the orientation of the magnetization vector of the soft magnetic layer. As a result, the magnetization vector of the hard magnetic layer and the soft magnetic layer will be changed from one type of alignment, e.g. “parallel alignment”, to the other type of alignment, e.g. “antiparallel alignment”, so that a data signal in form of one data bit can be recorded in the memory cell.

In MRAM structure design, lower writing power dissipation and a higher cell density are desired. Unfortunately, a reduction of cell size, i.e. an increase in cell density, leads to a reduction in the available energy (K_(u)V) to store the bit data. Further, the error rate increases as the cell size scales down. In order to reduce the error rate, high anisotropy energy is required to overcome thermal fluctuations. Hard magnetic material has higher anisotropy energy compared with soft magnetic material, but in that case a higher writing current is required. The higher anisotropy energy results in higher writing current density, which unfortunately has the disadvantage of electro-migration.

In order to reduce the writing current for a high coercitivity MRAM, thermally assisted MRAMs are disclosed. Un-pinned ferromagnetic materials, in which the coercitivity decreases sharply as temperature increases, are used for the recording layer in the MRAMs.

Another type of MRAM is spin-transfer torque memory (STRAM). STRAM utilizes electron spin torque to switch the free layer by passing a spin polarized current thorough the STRAM. STRAM has a higher efficiency as the memory cells scale down, but still suffers from the same issues as other MRAM cells as STRAM scales down. STRAM can also utilize thermal assist concept to reduce the switching current and maintain data retention time.

However, thermally assisted MRAM suffer from low heating efficiency. In addition, due to Joule heating, heat gradually builds in the memory array structure which increases the temperature of the memory device during operation.

BRIEF SUMMARY

The present disclosure relates to thermally assisted MRAM that includes phonon glass electron crystal material. In particular, the present disclosure relates to thermally assisted MRAM that utilize phonon glass electron crystal material to confine heat within the MRAM. The present disclosure relates to thermally assisted MRAM that utilize two different materials that generate a Peltier effect that assists in heating and cooling the MRAM cell.

One illustrative magnetic memory unit includes a tunneling barrier separating a free magnetic element and a reference magnetic element. A first phonon glass electron crystal layer is disposed on a side opposing the tunneling barrier of either the free magnetic element or the reference magnetic element.

One illustrative method includes applying a first current through a magnetic memory unit in a first direction. The magnetic memory unit includes a magnetic tunnel junction separating a first phonon glass electron crystal layer and a second phonon glass electron crystal layer. The first current causing a first interface between the magnetic tunnel junction and the first phonon glass electron crystal layer and a second interface between the magnetic tunnel junction and the second phonon glass electron crystal layer to generate heat. The method then includes applying a second current through the magnetic memory unit in a second direction opposing the first direction. The second current causing the first interface and the second interface to absorb heat.

BRIEF DESCRIPTION OF THE DRAWINGS

The disclosure may be more completely understood in consideration of the following detailed description of various embodiments of the disclosure in connection with the accompanying drawings, in which:

FIG. 1 is a schematic side view of an exemplary MRAM memory unit that utilizes external magnetic fields;

FIG. 2 is a schematic side view of another exemplary MRAM memory unit that utilizes spin-torque transfer;

FIG. 3 is a graph of current verses time for an exemplary MRAM memory unit; and

FIG. 4 is a flow diagram of an illustrative method.

The figures are not necessarily to scale. Like numbers used in the figures refer to like components. However, it will be understood that the use of a number to refer to a component in a given figure is not intended to limit the component in another figure labeled with the same number.

DETAILED DESCRIPTION

In the following description, reference is made to the accompanying set of drawings that form a part hereof and in which are shown by way of illustration several specific embodiments. It is to be understood that other embodiments are contemplated and may be made without departing from the scope or spirit of the present disclosure. The following detailed description, therefore, is not to be taken in a limiting sense. The definitions provided herein are to facilitate understanding of certain terms used frequently herein and are not meant to limit the scope of the present disclosure.

Unless otherwise indicated, all numbers expressing feature sizes, amounts, and physical properties used in the specification and claims are to be understood as being modified in all instances by the term “about.” Accordingly, unless indicated to the contrary, the numerical parameters set forth in the foregoing specification and attached claims are approximations that can vary depending upon the desired properties sought to be obtained by those skilled in the art utilizing the teachings disclosed herein.

The recitation of numerical ranges by endpoints includes all numbers subsumed within that range (e.g. 1 to 5 includes 1, 1.5, 2, 2.75, 3, 3.80, 4, and 5) and any range within that range.

As used in this specification and the appended claims, the singular forms “a”, “an”, and “the” encompass embodiments having plural referents, unless the content clearly dictates otherwise. As used in this specification and the appended claims, the term “or” is generally employed in its sense including “and/or” unless the content clearly dictates otherwise.

The present disclosure relates to thermally assisted MRAM that includes phonon glass electron crystal material. In particular, the present disclosure relates to thermally assisted MRAM that utilize phonon glass electron crystal material to confine heat within the MRAM. The present disclosure relates to thermally assisted MRAM that utilize two different materials that generate a Peltier effect that assists in heating and cooling the MRAM cell While the present disclosure is not so limited, an appreciation of various aspects of the disclosure will be gained through a discussion of the examples provided below.

FIG. 1 is a schematic side view of an exemplary magnetic memory (MRAM) unit 10 and FIG. 2 is a schematic side view of an exemplary MRAM unit 30. The MRAM memory unit 10 includes a reference magnetic element 20, a free magnetic element 30 and a tunneling barrier 25 separating the reference magnetic element 20 from the free magnetic element 30. These elements or layers are disposed electrically between a first electrode 12 and a second electrode 14 forming a magnetic tunnel junction 26. While a single MRAM memory unit 10 is shown, it is understood that a plurality of MRAM memory units 10 can be arranged in an array to form a memory array.

An access transistor 16 is electrically connected to the first electrode 12. The access or select transistor 16 can be electrically coupled to a sourceline SL and a wordline WL, for example. The access transistor 16 can be any useful transistor such as, for example, a NMOS or PMOS device. The access transistor 16 can provide a reading current, a cooling current, and a heating current to the magnetic tunnel junction 26.

The reference magnetic element 20 can include, at least, a reference ferromagnetic layer 21 and a reference antiferromagnetic layer 22. The reference antiferromagnetic layer 22 serves to fix the magnetization of the reference ferromagnetic layer 21. The reference magnetic element 20 has a blocking temperature (i.e., critical temperature) that is substantially the Curie temperature of the reference magnetic element 20. The blocking temperature of the reference antiferromagnetic layer 22 is the temperature at or above which the reference antiferromagnetic layer 22 loses its ability to pin (i.e., fix) the magnetization orientation of the adjacent reference ferromagnetic layer 21. In many embodiments, the blocking temperature is above 250 degrees centigrade or in a range from 200 to 350 degrees centigrade. In some embodiments, the reference magnetic element 20 includes more than one ferromagnetic layer that are coupled anti-ferromagnetically to each other (e.g., synthetic antiferromagnet). The synthetic antiferromagnet structure of the reference magnetic element 20 can reduce stray magnetic field interactions with the free magnetic element 30. The reference ferromagnetic layer 21 can be formed of any useful material such as, for example, alloys and materials including Co, Fe, and/or Ni. The reference antiferromagnetic layer 22 can be formed of any useful material such as, for example, IrMn, FeMn, and/or PtMn.

The free magnetic element 30 can include, at least, a free ferromagnetic layer 31 and a free antiferromagnetic layer 32. The free antiferromagnetic layer 32 serves to fix the magnetization of the free ferromagnetic layer 31. The free magnetic element 30 has a blocking temperature (i.e., critical temperature) that is substantially the Curie temperature of the free magnetic element 30. The blocking temperature of the free antiferromagnetic layer 32 is the temperature at or above which the free antiferromagnetic layer 32 loses its ability to pin (i.e., fix) the magnetization orientation of the adjacent free ferromagnetic layer 31. In many embodiments, the blocking temperature of the free antiferromagnetic layer 32 is less than the blocking temperature of the reference antiferromagnetic layer 22. In many embodiments, the blocking temperature of the free antiferromagnetic layer 32 is less than 150 degrees centigrade or in a range from 50 to 150 degrees centigrade. In some embodiments, the free magnetic element 30 includes more than one ferromagnetic layer that are coupled anti-ferromagnetically to each other (e.g., synthetic antiferromagnet). The synthetic antiferromagnet structure of the free magnetic element 30 can reduce stray magnetic field interactions with the reference magnetic element 20. The free ferromagnetic layer 31 can be formed of any useful material such as, for example, alloys and materials including Co, Fe, and/or Ni. The free antiferromagnetic layer 32 can be formed of any useful material such as, for example, IrMn, FeMn, and/or PtMn.

The tunneling barrier 25 separates the free magnetic element 30 from the reference magnetic element 20. The tunneling barrier 25 is an electrically insulating and non-magnetic material. The tunneling barrier 25 can be formed of any useful electrically insulating and non-magnetic material such as, AlO, MgO, and/or TiO, for example.

The magnetic memory unit 10 includes phonon glass electron crystal layers 41, 42 disposed adjacent to the free magnetic element 30 or the reference magnetic element 20. In the illustrated embodiment, a first phonon glass electron crystal layer 41 is adjacent to free magnetic element 30 and a second phonon glass electron crystal layer 42 is adjacent to the reference magnetic element 20. In many embodiments, the first phonon glass electron crystal layer 41 separates the free magnetic element 30 from the second electrode 14 and the second phonon glass electron crystal layer 42 separates the reference magnetic element 20 from the reference magnetic element 20.

The phonon glass electron crystal material forming the layer 41, 42 is electrically conducting but thermally insulating. In other words, phonon glass electron crystal material possesses good electronic transport properties of a crystal and resists the passage of heat as well as glass does. For example, the phonon glass electron crystal material forming the layer 41, 42 has a thermal conductivity of less than 10 W/m-K and an electrical area resistance of less than 100 Ohm/μm2. Thus, the phonon glass electron crystal material reduces or prevent heat from passing through the phonon glass electron crystal material. This can increase energy efficiency when heating the magnetic memory cell for thermally assisted writing operations.

The phonon glass electron crystal layer can be formed of any useful material possessing the electrically conducting but thermally insulating properties described above. In many embodiments, the phonon glass electron crystal layer is a superlattice structure formed of an alloy of BiTeSe, CoAs, CeCoFeSb, SiGeC/Si, Bi₂Te₃/Sb₂Te₃ or X₈Y₁₆Z₃₀ where X is Ba, Sr, or Eu; Y is Al, Ga or In; and Y is Si, Ge or Sn.

In many embodiments, the phonon glass electron crystal layer provides a Peltier effect on the magnetic tunnel junction when a current flows through the memory unit. When a current passes through the memory unit having an n type phonon glass electron crystal layer and an opposing p type phonon glass electron crystal layer sandwiching the magnetic tunnel junction, the current causes the interfaces between the magnetic tunnel junction and the phonon glass electron crystal layers to either generate heat or absorb heat, depending on the direction of the current.

For example, when applying a first current through a magnetic memory unit in a first direction, where the magnetic memory unit includes a magnetic tunnel junction separating a first phonon glass electron crystal layer and a second phonon glass electron crystal layer, the first current causes an interface between the magnetic tunnel junction and the first phonon glass electron crystal layer and the second phonon glass electron crystal layer to generate heat. Electrons in an n type phonon glass electron crystal layer will move opposite the direction of the current and holes in the p type phonon glass electron crystal layer will move in the direction of the current, both removing heat from one side of the magnetic tunnel junction.

Likewise, when applying a second current through the magnetic memory unit in a second direction opposing the first direction, the second current causes an interface between the magnetic tunnel junction and the first phonon glass electron crystal layer and the second phonon glass electron crystal layer to absorb heat. P type silicon has a positive Peltier coefficient and n type silicon has a negative Peltier coefficient.

N type (n for negative) dopants for semiconductor substrates (e.g., phonon glass electron crystal material) include, phosphorus (P), arsenic (As), or antimony (Sb), boron (B) or aluminium (Al), for example. P type (P for positive) dopants are a certain type of atoms added to the semiconductor substrates (e.g., phonon glass electron crystal material) in order to increase the number of free charge carriers (in this case positive).

When the doping material is added to the semiconductor substrates (e.g., phonon glass electron crystal material), it takes away (accepts) weakly-bound outer electrons from the semiconductor atoms. This type of doping agent is also known as acceptor material and the semiconductor atoms that have lost an electron are known as holes.

The purpose of p type doping is to create an abundance of holes. In the case of silicon, a trivalent atom (often from group IIIA of the periodic table, such as boron or aluminium) is substituted into the crystal lattice. The result is that one electron is missing from one of the four covalent bonds normal for the silicon lattice. Thus the dopant atom can accept an electron from a neighboring atoms' covalent bond to complete the fourth bond. Such dopants are called acceptors. The dopant atom accepts an electron, causing the loss of half of one bond from the neighboring atom and resulting in the formation of a “hole”. Each hole is associated with a nearby negative-charged dopant ion, and the semiconductor remains electrically neutral as a whole. However, once each hole has wandered away into the lattice, one proton in the atom at the hole's location will be “exposed” and no longer cancelled by an electron. For this reason a hole behaves as a quantity of positive charge. When a sufficiently large number of acceptor atoms are added, the holes greatly outnumber the thermally-excited electrons. Thus, the holes are the majority carriers, while electrons are the minority carriers in p type materials.

An n type semiconductor (including phonon glass electron crystal material) is obtained by carrying out a process of doping, that is, by adding an impurity of valence-five elements to a valence-four semiconductor in order to increase the number of free charge carriers (in this case negative). When the doping material is added, it gives away (donates) weakly-bound outer electrons to the semiconductor atoms. This type of doping agent is also known as donor material since it gives away some of its electrons.

The purpose of n type doping is to produce an abundance of mobile or “carrier” electrons in the material. To help understand how n type doping is accomplished, consider the case of silicon (Si). Si atoms have four valence electrons, each of which is covalently bonded with each of the four adjacent Si atoms. If an atom with five valence electrons, such as those from group 15 (old group VA, a.k.a. nitrogen group) of the periodic table (e.g., phosphorus (P), arsenic (As), or antimony (Sb)), is incorporated into the crystal lattice in place of a Si atom, then that atom will have four covalent bonds and one unbonded electron. This extra electron is only weakly bound to the atom and can easily be excited into the conduction band. At normal temperatures, virtually all such electrons are excited into the conduction band. Since excitation of these electrons does not result in the formation of a hole, the number of electrons in such a material far exceeds the number of holes. In this case the electrons are the majority carriers and the holes are the minority carriers. Because the five-electron atoms have an extra electron to “donate”, they are called donor atoms. Note that each movable electron within the semiconductor (e.g., phonon glass electron crystal material) is not far from an immobile positive dopant ion, and the n doped material normally has a net electric charge of zero. In an n type semiconductor, the fermi level lies closer to the conduction band edge.

The magnetic memory cell 10, 30 is in the low resistance state when the magnetization orientation of the free magnetic layer 31 is parallel and in the same direction of the magnetization orientation of the reference magnetic layer 21. This is termed the low resistance state or “0” data state. The magnetic memory cell 10, 30 is in the high resistance state when the magnetization orientation of the free magnetic layer 31 is anti-parallel and in the opposite direction of the magnetization orientation of the reference magnetic layer 21. This is termed the high resistance state or “1” data state.

FIG. 1 is a schematic side view of an exemplary MRAM memory unit 10 that utilize external magnetic fields to switch the data state of the memory unit. The free magnetic element 30 has a magnetization orientation that is alterable or rotatable upon application of an external magnetic field (such as is produced by the first writing bit line WBL₁ and the second writing bit line WBL₂). A first writing bit line WBL₁ is electrically isolated from the memory stack 26 and passes close enough to the memory stack 26 so that its magnetic field generated by a current 13 passing thought the first writing bit line WBL₁ can alter the magnetization orientations of the recording magnetic layer 20 and/or the free magnetic layer 30. The first writing bit line WBL₁ longitudinally extends in a first direction.

A second writing bit line WBL₂ is electrically isolated from the memory stack 26 and passes close enough to the memory stack 26 so that its magnetic field generated by a current 11 passing thought the second writing bit line WBL₂ can alter the magnetization orientations of the recording magnetic layer 20 and the free magnetic layer 30. The second writing bit line WBL₂ longitudinally extends in a second direction and in many embodiments is orthogonal to the first direction.

FIG. 2 is a schematic side view of another exemplary MRAM memory unit 30 that utilize spin-torque transfer to switch the data state of the memory unit. Switching the resistance state (between a high and low resistance state) and hence the data state of the memory unit 30 via spin-transfer occurs when a current, passing through a magnetic layer of the memory unit 30, becomes spin polarized and imparts a spin torque on the free magnetic element 30 of the magnetic tunnel junction 26. When a sufficient spin torque is applied to the free magnetic element 30, the magnetization orientation of the free magnetic element 30 can be switched between two opposite directions and accordingly the magnetic memory cell 30 can be switched between the parallel state (i.e., low resistance state or “0” data state) and anti-parallel state (i.e., high resistance state or “1” data state) depending on the direction of the current.

FIG. 3 is a graph of current verses time for an exemplary MRAM memory unit. For example, a positive current flowing through the magnetic memory units, described above heats the magnetic tunnel junction 26 and a negative current flowing through the magnetic memory units, described above cools the magnetic tunnel junction 26. Thus, these magnetic memory configurations can be utilized with thermally assisted magnetic memory where the magnetic memory is heated to a temperature that reduces the switching field or current needed to switch the memory unit between the high and low resistance state. Then passing a current in the opposing direction removes heat from the magnetic tunnel junction and provides an expedited cool down of the magnetic tunnel junction.

FIG. 4 is a flow diagram of an illustrative method 100. The method includes applying a first current I1 in a first direction through a magnetic tunnel junction (MTJ) having a phonon glass electron crystal layer (PGEC) to generate heat at block 101 The first current can be sufficient to raise the temperature of a antiferromagnetic layer adjacent to the free magnetic layer above it blocking temperature. This reduces the electric field needed to switch the magnetization orientation of the free magnetic layer at block 102. The phonon glass electron crystal layer also improves the heating efficiency for the MTJ by confining the generated heat to the MTJ. Then the MTJ can be cooled down by applying a second current I2 in a second direction (opposing the first direction) through a magnetic tunnel junction (MTJ) to absorb heat at block 103. This active cool down increases the heat removal from the MTJ (since the phonon glass electron crystal layer reduces or prevents heat flow through the phonon glass electron crystal layer) reducing the write time and allows the read operation to proceed at block 104 when the MTJ is cooled down sufficiently.

Thus, embodiments of the MAGNETIC MEMORY WITH PHONON GLASS ELECTRON CRYSTAL MATERIAL are disclosed. The implementations described above and other implementations are within the scope of the following claims. One skilled in the art will appreciate that the present disclosure can be practiced with embodiments other than those disclosed. The disclosed embodiments are presented for purposes of illustration and not limitation, and the present invention is limited only by the claims that follow. 

What is claimed is:
 1. A magnetic memory unit, comprising: a first phonon glass electron crystal layer; a second phonon glass electron crystal layer; and a magnetic tunnel junction disposed between the first and second phonon glass electron crystal layers, the magnetic tunnel junction comprising a tunneling barrier separating a free magnetic element and a reference magnetic element.
 2. A magnetic memory unit according to claim 1, wherein the first phonon glass electron crystal layer is an N type phonon glass electron crystal layer and the second phonon glass electron crystal layer is a P type phonon glass electron crystal layer.
 3. A magnetic memory unit according to claim 1, wherein the first and second phonon glass electron crystal layers have a thermal conductivity of less than 10 W/mK and an electrical area resistance of less than 100 Ohm/μm².
 4. A magnetic memory unit according to claim 1, wherein the magnetic tunnel junction switches between a high resistance data state and a low resistance data state by passing a spin-polarized current though the magnetic tunnel junction
 5. A magnetic memory unit according to claim 1, wherein the first and second phonon glass electron crystal layer each independently comprise an alloy of BiTeSe, CoAs, CeCoFeSb, SiGeC/Si, Bi₂Te₃/Sb₂Te₃ or X₈Y₁₆Z₃₀ where X is Ba, Sr, or Eu, Y is Al, Ga or In, and Z is Si, Ge or Sn.
 6. A magnetic memory unit according to claim 1, wherein the reference magnetic element comprises a reference ferromagnetic layer and a reference antiferromagnetic layer having a reference blocking temperature, and the free magnetic element comprises a free ferromagnetic layer and a free antiferromagnetic layer having a free blocking temperature being less than the reference blocking temperature.
 7. A magnetic memory unit according to claim 1, wherein the first and second phonon glass electron crystal layers provide a Peltier effect on the magnetic tunnel junction when current flows through the magnetic memory unit.
 8. A memory unit, comprising: a tunneling barrier separating a free magnetic element and a reference magnetic element forming a magnetic tunnel junction; a first N type phonon glass electron crystal layer disposed adjacent to the free magnetic element; a second P type phonon glass electron crystal layer disposed adjacent to the reference magnetic element; and a first electrode is coupled to the first N type phonon glass electron crystal layer and a second electrode is coupled to the second P type phonon glass electron crystal layer.
 9. A memory unit according to claim 8, wherein the first and second phonon glass electron crystal layers have a thermal conductivity of less than 10 W/mK and an electrical area resistance of less than 100 Ohm/μm².
 10. A memory unit according to claim 8, wherein the magnetic tunnel junction switches between a high resistance data state and a low resistance data state by passing a spin-polarized current though the magnetic tunnel junction.
 11. A memory unit according to claim 8, wherein the magnetic tunnel junction switches between a high resistance data state and a low resistance data state by applying an external magnetic field though the magnetic tunnel junction.
 12. A memory unit according to claim 8, wherein the first and second phonon glass electron crystal layers each independently comprise BiTeSe, CoAs, CeCoFeSb, SiGeC/Si, Bi₂Te₃/Sb₂Te₃ or X₈Y₁₆Z₃₀ where X is Ba, Sr, or Eu, Y is Al, Ga or In, and Z is Si, Ge or Sn.
 13. A memory unit according to claim 8, wherein the reference magnetic element comprises a reference ferromagnetic layer and a reference antiferromagnetic layer having a reference blocking temperature, and the free magnetic element comprises a free ferromagnetic layer and a free antiferromagnetic layer having a free blocking temperature being less than the reference blocking temperature.
 14. A memory unit according to claim 8, wherein an interface of the first phonon glass electron crystal layer and the magnetic tunnel junction generates heat when a first current is applied through the first phonon glass electron crystal layer and the magnetic tunnel junction and the interface of the first phonon glass electron crystal layer and the magnetic tunnel junction absorbs heat when a second opposing current being is applied through the first phonon glass electron crystal layer and the magnetic tunnel junction.
 15. A memory unit according to claim 14, wherein an interface of the second phonon glass electron crystal layer and the magnetic tunnel junction generates heat when the first current is applied through the first phonon glass electron crystal layer and the magnetic tunnel junction and the interface of the second phonon glass electron crystal layer and the magnetic tunnel junction absorbs heat when the second opposing current being is applied through the second phonon glass electron crystal layer and the magnetic tunnel junction.
 16. A memory unit, comprising: a tunneling barrier separating a free magnetic element and a reference magnetic element forming a magnetic tunnel junction; a first P type phonon glass electron crystal layer disposed adjacent to the free magnetic element; a second N type phonon glass electron crystal layer disposed adjacent to the reference magnetic element; and a first electrode is coupled to the first P type phonon glass electron crystal layer and a second electrode is coupled to the second N type phonon glass electron crystal layer.
 17. A memory unit according to claim 16, wherein the first and second phonon glass electron crystal layers have a thermal conductivity of less than 10 W/mK and an electrical area resistance of less than 100 Ohm/μm².
 18. A memory unit according to claim 16, wherein the magnetic tunnel junction switches between a high resistance data state and a low resistance data state by passing a spin-polarized current though the magnetic tunnel junction.
 19. A memory unit according to claim 16, wherein the magnetic tunnel junction switches between a high resistance data state and a low resistance data state by applying an external magnetic field though the magnetic tunnel junction.
 20. A memory unit according to claim 16, wherein the first and second phonon glass electron crystal layers each independently comprise BiTeSe, CoAs, CeCoFeSb, SiGeC/Si, Bi₂Te₃/Sb₂Te₃ or X₈Y₁₆Z₃₀ where X is Ba, Sr, or Eu, Y is Al, Ga or In, and Z is Si, Ge or Sn. 